The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a package substrate provided with through-holes as well as a fabrication process thereof.
There is a known construction of semiconductor device having a resin package body in which a semiconductor chip is held on a multilayer package substrate in the form of bare chip. In such a semiconductor device, the package substrate, typically formed of glass epoxy, carries electrodes on an upper major surface thereof for electrical contact with the semiconductor chip. Further, there are provided electrodes on a lower major surface of the package substrate for electrical contact with external circuits such as a printed circuit board. Thereby, the electrodes on the upper major surface of the package substrate are electrically connected to corresponding electrodes on the lower major surface of the package substrate by way of through-holes that penetrate through the package substrate from the upper major surface to the lower major surface.
With increasing integration density of the semiconductor integrated circuits, there is a tendency that the number of the electrode pads on a semiconductor chip increases. As the foregoing electrodes on the upper as well as lower major surfaces of the package substrate are provided in correspondence to the electrode pads on the semiconductor chip, the number of the electrodes as well as the number of the through-holes on the package substrate increase with increasing number of the electrode pads on the semiconductor chip. Thus, there arises a contradiction between the requirement to increase the number of the electrode pads on the semiconductor chip as much as possible in correspondence to the increased integration density and the requirement to reduce the package size as much as possible.
FIGS. 1-3 show a conventional semiconductor device 1 wherein FIG. 1 shows a part of the semiconductor device 1 in an elevational cross sectional view in an enlarged scale.
Referring to FIG. 1, it will be noted that the semiconductor device is primarily formed of a semiconductor chip. 2 and a package substrate 3 that supports the semiconductor chip 2 thereon. The package substrate 3 has a three-layered structure including layer elements 3.sub.-1 -3.sub.-3 for realizing increased density of electrodes. More specifically, the layer element 3.sub.-3 at the lowermost level physically supports the semiconductor chip 2. Typically, the semiconductor chip 2 is mounted upon the layer element 3.sub.-3 by means of adhesive.
The layer element 3.sub.-2 is provided upon the layer element 3.sub.-3 and includes an opening 4 for accommodating the semiconductor chip 2. Further, the layer element 3.sub.-1 on the layer element 3.sub.-2 includes another opening 5 in correspondence to the opening 4 for accommodating the semiconductor chip 2, wherein the opening 5 has an area larger than the area of the opening 4, and there is provided a step between the layer element 3.sub.-2 and the layer element 3.sub.-1.
It should be noted that the package substrate 3 is formed of a number of through-holes penetrating from the upper major surface of the layer element 3.sub.-1 to the lower major surface of the layer element 3.sub.-3, and a conductive member such as a copper plug or sleeve fills the through-holes 9. Thereby, the through-holes 9 provide an electrical path for connecting the electrodes on the upper major surface and the electrodes on the lower major surface of the package substrate 3.
As indicated in FIGS. 2 and 3, there are provided electrodes 7 on the upper major surface of the layer element 3.sub.-2 along the peripheral edge of the opening 4 for connection with electrode pads 6 on the semiconductor chip 2. Similarly, there are provided electrodes 8 on the upper major surface of the layer element 3.sub.-1 along the peripheral edge of the opening 5 for connection with other electrode pads 6 on the semiconductor chip 2. The contact electrodes 7 and 8 are thereby connected to the corresponding electrode pads 6 on the semiconductor chip 2 by way of bonding wires 9a and 10.
Further, the electrodes 7 on the layer element 3.sub.-2 and the electrodes 8 on the layer element 3.sub.-8 are connected to respective, corresponding through-holes 9 shown in FIGS. 2 and 3 by solid circles, by way of conductor patterns 10.sub.-1 and 10.sub.-2 that are provided respectively on the layer elements 3.sub.-1 and 3.sub.-2. In other words, the conventional semiconductor device of FIGS. 1-3 achieves the mounting of high integration density semiconductor chip on a small package body by constructing the package substrate 3 from the layer elements 3.sub.-1 -3.sub.-3 and by forming the conductor patterns 10.sub.-1 and 10.sub.-2 respectively on the layer elements 3.sub.-1 and 3.sub.-2.
In the conventional semiconductor device 1 of FIGS. 1-3, it is necessary to form the conductor patterns 10.sub.-1 and 10.sub.-2 such that the conductor patterns 10.sub.-1 and 10.sub.-2 avoid the through-holes 9 that penetrate through the package substrate 3. Thus, while it is necessary in the semiconductor devices having a high integration density to provide a large number of through-holes 9, such an increase in the number and hence the density of the through-holes 9 inevitably invites an increased area of the package substrate 3 that is occupied by the through holes 9. Thereby, there arises a difficulty in providing the necessary conductor patterns 10.sub.-1 and 10.sub.-2 on the respective layer elements. Further, the degree of freedom for providing the conductor patterns 10.sub.-1 and 10.sub.-2 is substantially reduced and there arises a case in which the connection of an electrode pad on the semiconductor chip 2 to a corresponding through-hole becomes difficult. In order to avoid the foregoing problem, it is necessary to increase the area of the layer elements 3.sub.-1 -3.sub.-3 and hence the size of the package substrate 3, while such an increase in the size of the package substrate 3 contradicts with the requirement to reduce the size of the package body of the semiconductor device.
Associated with the foregoing problem, there further arises a difficulty in the conventional semiconductor device in that two of the conductor patterns 10.sub.-1 or 10.sub.-2 come excessively close with each other in the vicinity of the through holes 9 and cause an electrical interference or crosstalk. When such an interference occurs, the risk of malfunctioning of the semiconductor device increases substantially.